In the field of portable electronic devices, it is known to enable freedom from tethering to a mains power source by providing a portable electronic device with a capability to use batteries or fuel cells, either disposable or rechargeable.
Consequently, an important consideration in relation to the portable device is power consumption as this impacts upon how quickly the energy of the battery is depleted and hence the amount of time for which the portable device can be used.
Despite gradual improvements in recent decades, battery technology has not kept pace with power consumption demands of the latest portable electronic devices, like handheld computing devices and third generation (3G) mobile phones. Hardware designers are therefore using advanced power—saving mechanisms to help minimise Integrated Circuit (IC) and system power consumption.
In this respect, new generations of applications processors, baseband processors, power management ICs and other platform components now include the advanced power management hardware mechanisms, for example Dynamic Frequency Scaling (DFS), Dynamic Voltage Scaling (DVS), and multiple idle modes such as so-called “Wait”, “Deep Sleep” and/or “Hibernate” modes. Power reduction and energy conservation is achieved by placing hardware blocks into lower power states, where performance is also lower or non-existent. To do this dynamically while programs are running requires an accurate knowledge of ever-changing workload that software being executed requires of various blocks of hardware making up the portable device, for example a processor and/or peripherals. Therefore, most of the above mechanisms do not yield significant energy conservation, and thus better battery life, unless intelligent software is used to exploit effectively the power-saving techniques built into the hardware.
Energy-Conserving Software (ECS) uses predictive and/or a priori techniques to determine the varying run-time workload needed by the processor (or processors) and other Power-Managed Components (PMCs), i.e. programmable hardware modules, within a real-time embedded electronic system. The ECS uses the workload estimations to set Performance-Power (PP) settings (or states) of the PMCs dynamically to levels high enough to deliver instantaneous performance needed to process the workload in time to meet real-time deadlines, but no higher than necessary, thereby minimising power wastage.
It therefore follows, in relation to the processor, that the PP states, for example operating clock frequency and operating voltage, of the processor ideally should be set just high enough to ensure that application programs and other critical software execute fast enough to meet real-time processing deadlines, but not higher than necessary, thereby avoiding wastage of power. Time leading up to the real-time deadline not required for workload processing constitutes so-called slack-time during which energy-saving measures, through setting of the PP states, can potentially be invoked. Further, for optimal energy conservation the PP states should be set in real-time as the workload, for example a software program, is being processed.
Unfortunately, there are penalties or ‘costs’ in both power consumption and time in transitioning between PP states of a given piece of hardware. These costs can easily outweigh the (energy-saving) benefits of the PP state to be used and so for optimal energy conservation some cost-benefit analysis should be performed in real-time to qualify a decision as to whether or not (and when) to make a particular transition to a potentially energy-saving PP state. Such cost-benefit analysis is described for various PP mechanisms, such as shutdown or idle modes, in public domain literature, for example: “A Survey of Design Techniques for System-Level Dynamic Power Management” (L. Benini, A. Bogliolo, G. De Micheli, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 3, June 2000), “Energy-Conscious, Deterministic I/O Device Scheduling in Hard Real-Time Systems” (V. Swaminathan, K. Chakrabarty, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 22, No. 7, July 2003), or “Improving Energy Saving in Wireless Systems by Using Dynamic Power Management” (C. Chiasserini, R. R. Rao, IEEE Transactions On Wireless Communications, Vol. 2, No. 5, September 2003). However, in some energy conservation implementations no cost-benefit analysis is performed. Further, when present, the cost-benefit qualification is specific to a particular power-saving design employed by, and the fabrication characteristics of, the PP mechanism, i.e. a hardware-specific ad-hoc solution is employed that makes the ECS complex, hard to maintain and difficult to port to new hardware platforms.